Recently, there was an increase in the number of terminals and the narrowing of their pitches in the semiconductor or integrated circuit device which result from advancements in the performance of operations, the capability of performing multi tasks and the integration thereof, which results in the growing demands of the interconnecting substrate for packaging which carries the semiconductor device also attains a higher density in arrangement and interconnections.
The current interconnecting substrate for packaging in-use, which are made of build-up multi-layered substrate, a sort of multi-layered interconnecting substrate.
Glass epoxy print substrates which are used as the base core substrate, which build-up multi-layered substrate is fabricated by forming an epoxy resin layer on both surfaces of this glass epoxy print substrate. Then, forming via holes in these epoxy resin layers by means of photolithography or laser. After that, plating method and the photolithography with a combination of the electroless or electrolytic Cu, in which an interconnection layer and via conductors are formed such that the formation of build-up layered structure is archived.
However, the glass epoxy print substrate may cause a problem that the heat treatments performed in fabrication of the build-up multi-layered substrate may bring the glass epoxy print substrate to a poor condition and creating defects. Furthermore, the heat treatments carried out at the time of chip loading and solder reflow may to cause the faulty connection and the distortion which effects the long-term reliability for the connection.
Moreover, the interconnecting substrate for packaging is mounted on an external board or apparatus, the stress is structurally centered on the interface between the external electrode terminal and the insulating layer, which tends to give rise to opening defects so that the satisfactory mounting reliability cannot be obtained.
Therefore the purpose of overcoming the above problems, there have been proposed an integrated circuit package and manufacturing method thereof, and more particularly to a carrierless-integrated circuit package having a covering means.